UDP Core Technical Report

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DOI	10.5286/stfctr.2024003
Persistent URL	http://purl.org/net/epubs/work/58860540
Record Status	Checked
Record Id	58860540
Title	UDP Core Technical Report
Contributors	Mr A. Barcock (STFC Rutherford Appleton Lab.), Mr S. Bolton, Mr A. Earle, Mr R. Halsall (STFC Rutherford Appleton Lab.), Mr J. Hindmarsh (STFC Rutherford Appleton Lab.), Mr S. Pradeep (STFC Rutherford Appleton Lab.), Mr M. Roberts (STFC Rutherford Appleton Lab.), Mr D. Templeman (STFC Rutherford Appleton Lab.)
Abstract	Bespoke data acquisition (DAQ) systems are developed to process the terabytes of raw data generated by modern high-energy physics (HEP) experiments. Field programmable gate arrays (FPGA) and multi-gigabit Ethernet are two prevalent technologies used in HEP DAQ systems. This report presents a VHDL implementation of a UDP packet engine called the UDP Core. A full network stack can be implemented in FPGA by combining the UDP Core with an Ethernet MAC and PHY. The UDP Core currently scales to support one, ten, forty and one-hundred gigabit Ethernet standards used in HEP experiments. This report presents the architecture of the UDP Core, the results of testing in FPGA, and potential future developments.
Organisation	TECH , STFC
Keywords
Funding Information
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Licence Information:	Creative Commons Attribution 4.0 International (CC BY 4.0)
Language	English (EN)

Type	Details	URI(s)	Local file(s)	Year
Report	STFC Technical Reports STFC-TR-2024-003. STFC, 2024.		STFC-TR-2024-003.pdf	2024