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Persistent URL http://purl.org/net/epubs/work/60115996
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Record Id 60115996
Title Architecture for error detection and recovery in MPSoCs: A Hypervisor approach using Dynamic Partial Reconfiguration
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Abstract
Organisation ISIS , STFC , ISIS-CHIPIR
Keywords virtual machine monitors , dynamic partial reconfiguration , fault tolerance , field programmable gate arrays , COTS , switches , coprocessors , MPSoC , FPGA , radiation , computer architecture , hypervisor , protons , redundancy , logic , hardware , error correction
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Language English (EN)
Type Details URI(s) Local file(s) Year
Journal Article IEEE Trans Nucl Sci (2025): 1-1. doi:10.1109/TNS.2025.3534431 2025