A blocked implementation of Level 3 BLAS for RISC Processors

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Persistent URL	http://purl.org/net/epubs/work/33035
Record Status	Checked
Record Id	33035
Title	A blocked implementation of Level 3 BLAS for RISC Processors
Contributors	MJ Daydé (CCLRC Rutherford Appleton Lab.), IS Duff (CCLRC Rutherford Appleton Lab.)
Abstract
Organisation	CCLRC , CSE , CSE-NAG
Keywords
Funding Information
Related Research Object(s):
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Language	English (EN)

Type	Details	URI(s)	Local file(s)	Year
Report	RAL Technical Reports RAL-TR-96-014. 1996.		RAL-TR-96-014.pdf	1996